1. Field of the Invention
The present invention relates to a semiconductor memory. It is particularly related to a miniaturized nonvolatile semiconductor memory encompassing a plurality of cell columns, each of the cell columns embraces serially connected plural memory cells, the cell columns being arranged very close to each other; and a fabrication method thereof.
2. Description of the Related Art
In recent years, usage of an alumina (Al2O3) film has been proposed for the material of an inter-electrode dielectric 4, which insulates a lower conductive layer (a floating gate electrode) 3 from an upper conductive layer (a control gate electrode) 7 as shown in FIG. 1A. FIG. 1A is a schematic cross sectional view showing part of a memory cell matrix cut along the column-direction, and one of memory cell transistors QCk in a k-th cell column, a select transistor QSGk in the cell column and another select transistor QSGk−1 in adjacent k−1-th column are shown, and FIG. 1B is a schematic cross sectional view showing a part of the memory cell matrix viewed along row-direction on the select transistor QSGk. For the double-polysilicon architecture encompassing a polysilicon floating gate electrode 3 and a polysilicon control gate electrode 7, the inter-electrode dielectric 4 is called “an interpoly dielectric”.
FIG. 1C is a schematic cross sectional view showing a peripheral transistor Qp in a peripheral site, cut along the column-direction. In the semiconductor memory having the memory cell transistors QCk implemented by a gate electrode structure, in which a lower conductive layer 3 and an upper conductive layer 7 are stacked via the inter-electrode dielectric 4, by a fabrication method forming a lower conductive layer 3 in a self-alignment methodology with respect to an active region, for both the memory cell site and the peripheral site, stacked structures of a gate insulator 2, the lower conductive layer (floating gate electrode) 3, the inter-electrode dielectric 4, and the upper conductive layer (control gate electrode) 7 can be formed. The gate insulator 2, the lower conductive layer 3, the inter-electrode dielectric 4, and the upper conductive layer 7 are all stacked in this order on the active region. However, in the architecture in which the peripheral transistor Qp belonging to the peripheral site is aligned continuously to an outermost positioned select transistor QSGk in a memory cell site, the problem of how to conductively connect the upper conductive layer (control gate electrode) 7 to the already formed lower conductive layer (floating gate electrode) 3 has become an issue.
A cell site gate insulator 2 requires a film thickness of approximately 10 nm for maintaining memory cell data-retaining characteristics when using a silicon oxide film, for example. Thus, for enhancing the performance of the peripheral transistor Qp of the peripheral site, the thickness of the peripheral site gate insulators 10 is required to be thinner than the thickness of the cell site gate insulators 2.
As a result of such circuit design necessities, in the earlier architecture, for the peripheral transistor Qp of the peripheral site, and for the select transistors QSGk and QSGk−1 in memory cell site, by removing the already formed lower conductive layer (floating gate electrode) 3, and then by exchanging it with new gate insulators, new gate electrodes are fabricated exclusively for the peripheral site and for the select transistors QSGk and QSGk−1. Namely, the peripheral transistor Qp of the peripheral site and the select transistors QSGk and QSGk−1 in the memory cell site, which do not have the lower conductive layer 3, have been separately fabricated from the memory cell transistors QCk in the memory cell site, which have the lower conductive layers 3 as disclosed in Japanese Patent Application Laid-open No. 2001168306.
However, with the earlier semiconductor memory and a fabrication method of the earlier semiconductor memory disclosed in Japanese Patent Application Laid-open No. 2001168306, finer and finer photolithography processes are necessary for removing upper conductive layer (control gate electrode) 7 of the select transistors QSGk and QSGk−1. That is, considering miniaturized dimensions and misalignment margins in photolithography processes for opening windows in the select transistors QSGk and QSGk−1, as well as the misalignment margins in the other photolithography processes for forming the select transistors QSGk and QSGk−1, the fabrication of the miniaturized select transistors QSGk and QSGk−1 becomes very difficult.